1. Field of the Invention
The present invention relates to a method of forming a dual damascene pattern in a semiconductor device, and more particularly, to a method of forming a dual damascene pattern in a semiconductor device capable of improving resolution of an exposure and development process for forming a photoresist pattern.
2. Background of the Related Art
Recently, as the semiconductor device is higher integrated while the design rule is thus reduced since the process technology is continuously advanced, parasitic capacitance between the wire resistors or the wires serves as a decisive factor in deciding the operation speed of the device. These days, a process of forming the metal wire using Cu in lieu of Al has been highlighted as a wiring process of a next generation device.
However, there is a difficulty in forming the wires using Cu since the etching characteristic of Cu is very poor. In order to solve this problem, the metal wire is formed using a metal material having a poor etching characteristic as well as Cu by means of a dual damascene process and an electroplating method. This dual damascene process will be now described in more detail.
FIG. 1(a)˜FIG. 1(d) are cross-sectional views of semiconductor devices for explaining a conventional method of forming a dual damascene pattern in the device.
Referring to FIG. 1(a), in order to form a semiconductor device, an interlayer insulating film 102 is formed on a semiconductor substrate 101 in which various components (not shown) such as a transistor or a flash memory cell are formed. A resist is then coated on the interlayer insulating film 102. Next, a first photoresist pattern 103 in which a trench region is defined is formed through exposure and development processes.
By reference to FIG. 1(b), the interlayer insulating film 102 in a region exposed through a first photoresist pattern (103 in FIG. 1(a)) is etched by a given depth, thereby forming a trench 104. The first photoresist pattern is then removed.
With reference to FIG. 1(c), a resist is coated on the interlayer insulating film 102. A second photoresist pattern 105 in which a via hole region is defined is formed through the exposure and development processes.
Turning to FIG. 1(d), the interlayer insulating film 102 in the region exposed through the second photoresist pattern (105 in FIG. 1(c)) is etched to form a via hole 106 through which the junction (not shown) at the bottom is exposed. Thereafter, the second photoresist pattern is removed. Thereby, a dual damascene pattern 107 consisting of the trench 104 and the via hole 106 is completed.
Hereinafter, although not shown in the drawings, in order to prevent metal component of the metal wire to be formed in a subsequent process from infiltrating into the interlayer insulating film, a barrier metal layer is formed on the interlayer insulating film, a metal seed layer is formed only within the via and trench, and the via and the trench are then buried with the metal material by an electroplating method, thus forming the metal wire. After the metal wire is formed, additional chemical mechanical polishing process is implemented to remove a thin metal film formed on the interlayer insulating film other than the via and trench.
As in the above, the dual damascene process for first forming the trench is simple and has a less problem in the etching process than the dual damascene process. Accordingly, this process has been recognized one of the methods having a high reproducibility. However, from the viewpoint of the lithography, the dual damascene process that first forms the trench then the via hole must form a second photoresist pattern for defining the via hole region with the step generated by the trench. For this reason, there is a problem that resolution is fatally influenced since the photoresist pattern is thickly formed in the trench region, as in FIG. 1(c). Accordingly, it is recently recognized that this process is rarely used since it is difficult to overcome the above problem.